The present invention relates to an improvement in the adder circuits suitable for LSIs as well as to an improvement in the layout structure of such adder circuits.
In recent years, LSIs have improved in the rate of operation as well as in the level of integration of elements. The speed-up of addition operations in the adder circuits is a great contribution to increasing the rate of LSI operation. Various schemes to implement fast addition operations have been proposed. For instance, adder circuits have been known in the art which employ a carry look ahead (CLA) circuit, one example of which is described below.
In a commonly-used adder circuit having a CLA circuit, at the time two numbers which contain a plurality of digits are added together a carry generation logic gi and a carry propagation logic pi are defined for every i digits, and a block carry propagation logic producing circuit capable of producing a block carry propagation logic and a block carry generation logic producing circuit capable of producing a block carry generation logic are formed by arrangement of gi and pi over a plurality of digits (bits). For example, when an addition operation of numbers A and B formed of n digits is performed, each digit""s carry generation and propagation logics gi and pi are given by the following equations.
pi=Ai+Bi
gi=Aixc2x7Bi
Hereinafter, these operators xe2x80x9c+xe2x80x9d, xe2x80x9cxc2x7xe2x80x9d, and xe2x80x9c/xe2x80x9d designate logical add, logical product, and logical inversion, respectively. A block carry generation logic G0 over three digits from digit 20 to digit 22 is given by the following equation.
G0=g2+p2xc2x7g1+p2xc2x7p1xc2x7g0xe2x80x83xe2x80x83(a)
If this logic G0 is constructed using CMOS circuits, then a structure, shown in FIG. 7, is obtained.
Referring to FIG. 7, whereas 501-506 are p-type metal-oxide-semiconductor (PMOS) transistors, 507-512 are n-type metal-oxide-semiconductor (NMOS) transistors. The source, gate, and drain of PMOS transistor 501 are coupled to VDD (the supply voltage), to the input g2, and to the sources of PMOS transistors 502 and 503, respectively. The gate and drain of PMOS transistor 502 are coupled to the input p2 and to the sources of PMOS transistors 504, 505, and 506, respectively. The gate and drain of PMOS transistor 503 are coupled to the input g1 and to the sources of PMOS transistors 504, 505, and 506, respectively. The gate and drain of PMOS transistor 504 are coupled to the input p1 and to the output node y, respectively. The gate and drain of PMOS transistor 505 are coupled to the input p2 and to the output node y, respectively. The gate and drain of PMOS transistor 506 are coupled to the input go and to the output node y, respectively.
The source, gate, and drain of NMOS transistor 507 are coupled to GND (ground), to the input g2, and to the output node y, respectively. The source, gate, and drain of NMOS transistor 508 are coupled to the drain of NMOS transistor 509, to the input g1, and to the output node y, respectively. The source, gate, and drain of NMOS transistor 509 are coupled to GND, to the input p2, and to the source of NMOS transistor 508, respectively. The source, gate, and drain of NMOS transistor 510 are coupled to the drain of NMOS transistor 511, to the input g0, and to the output node y, respectively. The source, gate, and drain of NMOS transistor 511 are coupled to the drain of NMOS transistor 512, to the input p2, and to the source of NMOS transistor 510, respectively. The source, gate, and drain of NMOS transistor 512 are coupled to GND, to the input p1, and to the source of NMOS transistor 511.
520 is a connection net for PMOS transistors 501, 502, and 503. 521 is a connection net for PMOS transistors 502, 503, 504, 505, and 506.
Referring to FIG. 7, a xe2x80x9c0xe2x80x9d is applied to the output node y if the NMOS transistor logic is g2+p2xc2x7g1+p2xc2x7p1xc2x7g0. In other cases the output node y is placed in the non-drive state.
On the other hand, a xe2x80x9c1xe2x80x9d is applied to the output node y if the PMOS transistor logic is /g2xc2x7(/p2+/g1)xc2x7(/p2+/p1+/g0). In other cases, the output node y is placed in the non-drive state. However, the PMOS transistor logic and the NMOS transistor logic are in a complementary relationship and, as a result, the output node y is driven to xe2x80x9c0xe2x80x9d or to xe2x80x9c1xe2x80x9d.
A block carry propagation logic P0 over three digits from digit 20 to digit 22 is given by the following equation.
P0=p2xc2x7p1xc2x7p0xe2x80x83xe2x80x83(b)
If this logic P0 is constructed using CMOS circuits, then a structure, shown in FIG. 9, is obtained.
Referring now to FIG. 9, whereas 600-602 are PMOS transistors, 603-605 are NMOS transistors. PMOS transistors 600-602 are coupled in parallel with one another. PMOS transistors 600-602 each have a terminal that is coupled to VDD and another terminal that is coupled to the output node y. The gate of PMOS transistor 600 is coupled to the input p0. The gate of PMOS transistor 601 is coupled to the input p1. The gate of PMOS transistor 602 is coupled to the input p2. On the other hand, NMOS transistors 603-605 are coupled in series with one another. The source and drain of NMOS transistor 605 is coupled to GND and to the source of NMOS transistor 604, respectively. The drain of NMOS transistor 604 is coupled to the source of NMOS transistor 603. The drain of NMOS transistor 603 is coupled to the output node y. The gate of NMOS transistor 603 is coupled to the input p2. The gate of NMOS transistor 604 is coupled to the input p1. The gate of NMOS transistor 605 is coupled to the input p0.
Referring to FIG. 8, a diagram as a result of laying out the logic of FIG. 7 is shown. FIG. 10 shows a diagram as a result of laying out the logic of FIG. 9. As can be seen from the logic of FIG. 7, in the PMOS transistor region two PMOS transistors (PMOS transistors 502, 503) are connected in parallel between VDD and the output node y and, in addition, three PMOS transistors (PMOS transistors 504, 505, 506), are also connected in parallel between VDD and the output node y. Because of such arrangement, there is produced the disadvantage that larger source and drain regions are required in the PMOS transistor formation area. This drawback is explained in detail. Referring to the FIG. 8 layout, the drain region of PMOS transistor 501 and each of the source regions of PMOS transistors 502 and 503 are connected together by the connection net 520, and each of the drain regions of PMOS transistors 502 and 503 and the source regions of PMOS transistors 504, 505, and 506 are connected together by the connection net 521. Since these connection nets 520 and 521 are connected with a first-level metallic layer, this requires the provision of contact regions 522 and 523 for establishing connections between the connection nets 520 and 521 and the source or drain regions of the foregoing PMOS transistors. The source or drain region of PMOS transistors extends, resulting in an increase in the capacitance and, and the operation delay increases.
As can be seen by reference to FIG. 7, formed over and under PMOS transistors 502 and 503 that are parallel-connected are PMOS transistors 501, 504, 505, and 506. Accordingly, it becomes necessary to divide an OD (oxide diffusion) region into two regions, namely a region 524 and a region 525. It further becomes necessary to form a free region between the regions 524 and 525. The size of the adder circuit increases by a proportional amount to such a free region.
On the other hand, in the NMOS transistor region two NMOS transistors, i.e., NMOS transistors 508 and 509, are connected in series between GND (ground) and the output node y, and, in addition, three NMOS transistors, i.e., NMOS transistors 510, 511, and 512, are also connected in series between GND and the output node y. This eliminates the need for the provision of connection nets. The foregoing drawback does not occur, accordingly.
As can be seen by making a comparison between the logic shown by Equation (a) and FIG. 7 and the logic shown by Equation (b) and FIG. 9, these logics differ from each other. Accordingly, the sharing of a block carry generation logic producing circuit and a block carry propagation logic producing circuit between these logics is impossible.
Accordingly, it is an object of the present invention to provide an improved adder circuit having a block carry generation logic producing circuit and a block carry propagation logic producing circuit which are small, fast, and mutually sharable, and a layout structure of such an adder circuit.
In order to provide a solution to the above-described problem, the present invention was made paying attention to the following points. If two binary numbers that contain nxe2x88x921 digits are represented respectively A and B, then the i-th digit""s carry propagation and generation logic values pi and gi are expressed by the following equations, respectively. Here, let n greater than i where the number i is an integer greater than xe2x80x9c0xe2x80x9d.                    pi        =                  Ai          +          Bi                                    (1-1)                                gi        =                  Ai          ·          Bi                                    (1-2)            
These operators xe2x80x9c+xe2x80x9d, xe2x80x9cxc2x7xe2x80x9d, and xe2x80x9c/xe2x80x9d designate logical add, logical product, and logical inversion, respectively. Using three consecutive digits (i=0, 1, 2) and Equations (1-1) and (1-2), carry generation logic values g0, g1, and g2 are generated from these three consecutive digits and carry propagation logic values p1 and p2 for the two high-order digits of the three consecutive digits are generated. By use of these five logic values g0, g1, g2, p1, and p2, a block carry generation logic value G0 and a block carry propagation logic value P0 both worth of three digits can be expressed by the following equations, respectively.                     G0        =                  g2          +                      p2            ·            g1                    +                      p2            ·            p1            ·            g0                                              (2-1)                                P0        =                  p2          ·          p1          ·          p0                                    (2-2)            
Since there exists a relationship between pi and gi shown by Equations (1-1) and (1-2), then the following relationships hold.                     pi        =                  pi          +          gi                                    (3-1)                                gi        =                  pi          ·          gi                                    (3-2)            
If Equation (2-1) is transformed using Equations (3-1) and (3-2), then the following equation (4) is obtained.                     G0        =                  g2          +                      p2            ·            g1                    +                      p2            ·            p1            ·            g0                                              (2-1)                                          /          G0                =                              /            p2                    +                                    /              g2                        ·                          /              p1                                +                                    /              g2                        ·                          /              g1                        ·                          /              g0                                                          (        4        )            
If Equation (2-2) is transformed using Equations (3-1) and (3-2), then the following equations (5-1) and (5-2) are obtained.                     P0        =                  p2          +                      g2            ·            p1                    +                      g2            ·            g1            ·            p0                                              (5-1)                                          /          P0                =                              /            g2                    +                                    /              p2                        ·                          /              g1                                +                                    /              p2                        ·                          /              p1                        ·                          /              p0                                                          (5-2)            
As can be seen from Equations (2-1) and (4), if the terms of the right side of Equation (2-1) are formed by NMOS transistors, then a xe2x80x9c0xe2x80x9d is applied to the output node y. If the terms of the right side of Equation (4) are formed by PMOS transistors, then a xe2x80x9c1xe2x80x9d is applied to the output node y. This makes it possible to constitute a CMOS logic of the block carry generation logic value G0. Further, as can be seen by comparison of Equation (2-1) with Equation (4), the logic of the terms of the right side of Equation (4) constructed of PMOS transistors is the same as the logic of the terms of the right side of Equation (2-1) constructed of NMOS transistors and has a logical product of two input values and a logical product of three input values. If the logic, expressed by Equation (4), is laid out, this results in a layout having a series connection constructed of two PMOS transistors and a series connection constructed of three PMOS transistors, whereby the overall PMOS transistor drain area can be reduced.
Additionally, as can be seen by making a comparison between Equations (5-1) and (5-2), the relationship between these Equations is the same as the relationship between Equations (2-1) and (4). If the logic, expressed by Equation (5-2), is laid out, this results in a layout having a series connection constructed of two PMOS transistors and a series connection constructed of three PMOS transistors, whereby the overall PMOS transistor drain area can be reduced.
Further, Equation (2-1) and Equation (5-1) are compared and the comparison result shows that they are identical in logic with each other, and Equation (4) and Equation (5-2) are compared and the comparison result shows that they are identical in logic with each other, from which it follows that the block carry generation logic producing circuit is identical in circuit organization with the block carry propagation logic producing circuit. Circuit sharing becomes feasible. As a result, producing block carry generation and propagation logics can be implemented by changing only input signals.
In accordance with the present invention, Equations (2-1), (4), (5-1), and (5-2) are used and the block carry generation logic G0 and the block carry propagation logic P0 are formed using CMOS circuits.
The present invention provides an adder circuit which is formed employing a plurality of n-type metal-oxide-semiconductor (NMOS) transistors and a plurality of p-type metal-oxide-semiconductor (PMOS) transistors and which performs addition of two numbers, each of said two numbers containing a plurality of digits,
said adder circuit including:
a block carry generation logic producing circuit for producing a block carry generation logic, G0, for consecutive n+1 or more digits of said two numbers at the time said two numbers are added together where the number n is any integer equal to or greater than two and for providing said logic G0 at an output node;
said block carry generation logic producing circuit including:
a first block carry generation logic producing section which is formed of said plurality of PMOS transistors and which has a logic that is expressed by the following equation:
/g0=/pn+/gnxc2x7/pnxe2x88x921+/gnxc2x7/gnxe2x88x921xc2x7/pnxe2x88x922 +/gnxc2x7/gnxe2x88x921xc2x7/gnxe2x88x922xc2x7/pnxe2x88x923+/gnxc2x7/gnxe2x88x921xc2x7/gnxe2x88x922xc2x7/gnxe2x88x923xc2x7/gnxe2x88x924
where the operator xe2x80x9c/xe2x80x9d designates logical inversion; and
a second block carry generation logic producing section which is formed of said plurality of NMOS transistors and which has a logic that is expressed by the following equation:
G0=gn+pnxc2x7gnxe2x88x921+pnxc2x7pnxe2x88x921xc2x7gnxe2x88x922 +pnxc2x7pnxe2x88x921xc2x7pnxe2x88x922xc2x7gnxe2x88x923+pnxc2x7pnxe2x88x921xc2x7pnxe2x88x922pnxe2x88x923xc2x7gnxe2x88x924 
It is preferred that said first block carry generation logic producing section includes:
a single PMOS transistor; and
a plurality of series circuits, each of said plurality of series circuits being formed of m PMOS transistors connected together in series where the number m is any integer ranging from two up to n+1;
wherein said single PMOS transistor and said series circuits each have a terminal which is coupled to a supply voltage and another terminal which is coupled to said output node and together form a PMOS transistor group in n+1 rows.
The present invention provides an adder circuit which is formed using a plurality of n-type metal-oxide-semiconductor (NMOS) transistors and a plurality of p-type metal-oxide-semiconductor (PMOS) transistors and which performs addition of two numbers, each of said two numbers containing a plurality of digits,
said adder circuit including:
a block carry propagation logic producing circuit for producing a block carry propagation logic, P0, for consecutive n+1 or more digits of said two numbers at the time said two numbers are added together where the number n is any integer equal to or greater than two and for providing said logic P0 at an output node;
said block carry propagation logic producing circuit including:
a first block carry propagation logic producing section which is formed of said plurality of PMOS transistors and which has a logic that is expressed by the following equation:
/P0=/gn+/pnxc2x7/gnxe2x88x921+/pnxc2x7/pnxe2x88x921xc2x7/gnxe2x88x922 +/pnxc2x7/pnxe2x88x921xc2x7/pnxe2x88x922xc2x7/gnxe2x88x923+/pnxc2x7/pnxe2x88x921xc2x7/pnxe2x88x922xc2x7/pnxe2x88x923xc2x7/pnxe2x88x924
where the operator xe2x80x9c/xe2x80x9d designates logical inversion; and
a second block carry propagation logic producing section which is formed of said plurality of NMOS transistors and which has a logic that is expressed by the following equation:
P0=pn+gnxc2x7pnxe2x88x921+gnxc2x7gnxe2x88x921xc2x7pnxe2x88x922 +gnxc2x7gnxe2x88x921xc2x7gnxe2x88x922xc2x7pnxe2x88x923+gnxc2x7gnxe2x88x921xc2x7gnxe2x88x922xc2x7gnxe2x88x923xc2x7pnxe2x88x924 
It is preferred that said first block carry propagation logic producing section includes a single PMOS transistor and a plurality of series circuits, each of said plurality of series circuits being formed of m PMOS transistors connected together in series where the number m is any integer ranging from two up to n+1 wherein said single PMOS transistor and said series circuits each have a terminal which is coupled to a supply voltage and another terminal which is coupled to said output node and together form a PMOS transistor group in n+1 rows.
The present invention provides an adder circuit which is formed using a plurality of n-type metal-oxide-semiconductor (NMOS) transistors and a plurality of p-type metal-oxide-semiconductor (PMOS) transistors and which performs addition of two numbers, each of said two numbers containing a plurality of digits,
(a) said adder circuit including:
a block carry generation logic producing circuit for producing a block carry generation logic, G0, for consecutive n+1 or more digits of said two numbers at the time said two numbers are added together where the number n is any integer equal to or greater than two and for providing said logic G0 at an output node; and
a block carry propagation logic producing circuit for producing a block carry propagation logic, P0, for consecutive n+1 or more digits of said two numbers at the time said two numbers are added together and for providing said logic P0 at said output node;
wherein:
a logic for producing said logic G0 in said block carry generation logic producing circuit is identical with a logic for producing said logic P0 in said block carry propagation logic producing circuit;
said logic for producing said logic G0 is expressed by the following equations:
G0=gn+pnxc2x7gnxe2x88x921+pnxc2x7pnxe2x88x921xc2x7gnxe2x88x922 +pnxc2x7pnxe2x88x921xc2x7pnxe2x88x922xc2x7gnxe2x88x923+pnxc2x7pnxe2x88x921xc2x7pnxe2x88x922xc2x7pnxe2x88x923xc2x7gnxe2x88x924
/G0=/pn+/gnxc2x7/pnxe2x88x921+/gnxc2x7/gnxe2x88x921xc2x7/pnxe2x88x922 +/gnxc2x7/gnxe2x88x921xc2x7/gnxe2x88x922xc2x7/pnxe2x88x923+/gnxc2x7/gnxe2x88x921xc2x7/gnxe2x88x922xc2x7/gnxe2x88x923xc2x7/gnxe2x88x924
where the operator xe2x80x9c/xe2x80x9d designates logic inversion; and
said logic for producing said logic P0 is expressed by the following equations:
P0=pn+gnxc2x7pnxe2x88x921+gnxc2x7gnxe2x88x921xc2x7pnxe2x88x922 +gnxc2x7gnxe2x88x921xc2x7gnxe2x88x922xc2x7pnxe2x88x923+gnxc2x7gnxe2x88x921xc2x7gnxe2x88x922xc2x7gnxe2x88x923xc2x7pnxe2x88x924
xe2x80x83/P0=/gn+/pnxc2x7/gnxe2x88x921+/pnxc2x7/pnxe2x88x921xc2x7/gnxe2x88x922 +/pnxc2x7/pnxe2x88x921xc2x7/pnxe2x88x922xc2x7/gnxe2x88x923+/pnxc2x7/pnxe2x88x921xc2x7/pnxe2x88x922xc2x7/pnxe2x88x923xc2x7/pnxe2x88x924
where the operator xe2x80x9c/xe2x80x9d designates logic inversion.
The present invention provides a layout structure for an adder circuit,
said adder circuit which is formed using a plurality of metal-oxide-semiconductor (MOS) transistors and which performs addition of two numbers, each of said two numbers containing a plurality of digits,
said adder circuit including:
a block carry generation logic producing circuit for producing a block carry generation logic for consecutive n+1 or more digits of said two numbers at the time said two numbers are added together where the number n is any integer equal to or greater than two and for providing said block carry generation logic at an output node;
said block carry generation logic producing circuit including:
a single MOS transistor; and
a plurality of series circuits, each of said plurality of series circuits being formed of m MOS transistors connected together in series where the number m is any integer ranging from two up to n+1;
wherein:
said single MOS transistor and said series circuits each have a terminal which is coupled to a supply voltage or to ground and another terminal which is coupled to said output node and together form a MOS transistor group in n+1 rows; and
in two series circuits of said plurality of series circuits, one of which is formed of the greatest number of series-connected MOS transistors and the other of which is formed of the second largest number of series-connected MOS transistors, MOS transistors of said two series circuits whose drain regions are coupled to said output node share a drain region.
The present invention provides a layout structure for an adder circuit,
said adder circuit which is formed using a plurality of metal-oxide-semiconductor (MOS) transistors and which performs addition of two numbers, each of said two numbers containing a plurality of digits,
said adder circuit including:
a block carry propagation logic producing circuit for producing a block carry propagation logic for consecutive n+1 or more digits of said two numbers at the time said two numbers are added together where the number n is any integer equal to or greater than two and for providing said block carry propagation logic at an output node;
said block carry propagation logic producing circuit including:
a single MOS transistor; and
a plurality of series circuits, each of said plurality of series circuits being formed of m MOS transistors connected together in series where the number m is any integer ranging from two up to n+1;
wherein:
said single MOS transistor and said series circuits each have a terminal which is coupled to a supply voltage or to ground and another terminal which is coupled to said output node and together form a MOS transistor group in n+1 rows; in two series circuits of said plurality of series circuits, one of which is formed of the greatest number of series-connected MOS transistors and the other of which is formed of the second largest number of series-connected MOS transistors, MOS transistors of said two series circuits whose drain regions are coupled to said output node share a drain region.
According to the above-described organization, in the adder circuit of the present invention a producing circuit for producing G0 (the block carry generation logic) uses a plurality of PMOS transistors to implement a logic expressed by the following equation.
/G0=/pn+/gnxc2x7/pnxe2x88x921+/gnxc2x7/gnxe2x88x921xc2x7/pnxe2x88x922 +/gnxc2x7/gnxe2x88x921xc2x7/gnxe2x88x922xc2x7/pnxe2x88x923+/gnxc2x7/gnxe2x88x921xc2x7/gnxe2x88x922xc2x7/gnxe2x88x923xc2x7/gnxe2x88x924
In addition, a producing circuit for producing P0 (the block carry propagation logic) uses a plurality of PMOS transistors to implement a logic expressed by the following equation.
/P0=/gn+/pnxc2x7/gnxe2x88x921+/pnxc2x7/pnxe2x88x921xc2x7/pnxe2x88x922 +/pnxc2x7/pnxe2x88x921xc2x7/pnxe2x88x922xc2x7/gnxe2x88x923+/pnxc2x7/pnxe2x88x921xc2x7/pnxe2x88x922xc2x7/pnxe2x88x923xc2x7/pnxe2x88x924
Such arrangement permits these PMOS transistors to form series connections each of which is constructed of a predetermined number of PMOS transistors, therefor eliminating the need for providing contact regions for forming connection between OD and metal layer. The drain region area of PMOS transistors can be reduced and the operation delay can be reduced. This achieves a small and fast adder circuit.
In the present adder circuit, the logic of producing a block carry generation logic and the logic of producing a block carry propagation logic are identical with each other. If a block carry generation logic producing circuit is constructed of a plurality of PMOS transistors and a plurality of NMOS transistors, this makes it possible to produce a block carry propagation logic by using such a circuit as it is as a block carry propagation logic producing circuit and by changing input signals to the circuit.
In accordance with a layout structure of an adder circuit of the present invention, in a series circuit that is formed of the largest number of series-connected MOS transistors and in a series circuit that is formed of the second largest number of series-connected MOS transistors, a common drain region is formed in order that in these series circuits MOS transistors with drain regions coupled to the output node may share a drain region. As a result of such arrangement, the drain region area of these MOS transistors can be reduced to a minimum. Delays in the operations can be reduced. This achieves a small and fast adder circuit.